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powerpc ? 750cxr risc microprocessor data sheet version: 1.2 (for dd4.0 only) february 28, 2005 ?
? ? copyright international business machines corporation 1991, 2005 all rights reserved printed in the united states of america 2/28/05 the following are trademarks of international business machines corporation in the united states, or other countries, or both. ibm ibm logo powerpc powerpc logo powerpc 750 other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation, life support, space, nuclear, or military applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an "as is " basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm system and technology group 2070 route 52, bldg. 330 hopewell junction, ny 12533-6351 the ibm home page can be found at: http://www.ibm.com the ibm microelectronics home page can be found at http://www.ibm.com/chips title.fm february 28, 2005
data sheet powerpc ? 750cxr risc microprocessor sw_ds_750cxrtoc.fm february 28, 2005 page 3 of 43 contents 1. general information .................................................................................................... 9 1.1 features .................................................................................................................. ......................... 9 1.2 special design level considerations /features ......................................................................... 11 1.3 ordering information ...................................................................................................... .............. 11 1.4 processor version register (pvr) .......................................................................................... .... 12 2. overview ................................................................................................................... . 13 2.1 powerpc 750cxr block diagram .............................................................................................. ... 13 3. general parameters .................................................................................................. 14 4. electrical and thermal characteristics ................................................................... 15 4.1 dc electrical characteristics ............................................................................................. .......... 15 4.2 ac electrical characteristics ............................................................................................. .......... 19 4.2.1 clock ac specifications ................................................................................................. ....... 19 4.3 spread spectrum clock generator (sscg) ................................................................................ 20 4.4 60x bus input ac specifications ........................................................................................... ...... 21 4.5 60x bus output ac specifications .......................................................................................... .... 22 4.5.1 ieee 1149.1 ac timing specifications ................................................................................. 25 5. powerpc 750cxr dimension and physical signal assignments ......................... 27 6. system design information ..................................................................................... 35 6.1 pll configuration ......................................................................................................... ................ 35 6.2 pll power supply filtering ................................................................................................ ......... 36 6.3 decoupling recommendations ................................................................................................ ... 36 6.4 connection recommendations ................................................................................................ ... 37 6.5 output buffer dc impedance ................................................................................................ ....... 37 6.5.1 input-output usage ...................................................................................................... ......... 38 6.6 thermal management information ............................................................................................ .. 41 6.6.1 thermal assist unit ..................................................................................................... .......... 41 6.6.2 heat sink considerations ................................................................................................ ...... 41 6.6.3 internal package conduction resistance .............................................................................. 42 6.7 operational and design considerations ..................................................................................... 42 6.7.1 level protection ........................................................................................................ ............. 42 6.7.2 64- or 32-bit data bus mode ............................................................................................. .... 43 6.7.3 60x bus operation ....................................................................................................... .......... 43 6.7.4 d bwo /l2_tstclk ............................................................................................................... 43 6.7.5 chkstp_out /clkout ....................................................................................................... 43 revision log ................................................................................................................ 45
data sheet powerpc ? 750cxr risc microprocessor page 4 of 43 sw_ds_750cxrtoc.fm february 28, 2005
data sheet powerpc ? 750cxr risc microprocessor sw_ds_750cxrlot.fm february 28, 2005 page 5 of 43 tables table 1-1. process version register (pvr) ...................................................................................... ........... 12 table 3-1. general parameters .................................................................................................. .................. 14 table 4-1. absolute maximum ratings ............................................................................................ ............. 15 table 4-2. recommended operating conditions .................................................................................... ..... 15 table 4-3. package thermal characteristics ..................................................................................... .......... 16 table 4-4. dc electrical specifications ........................................................................................ ................ 16 table 4-5. power consumption ................................................................................................... ................. 17 table 4-6. clock ac timing specifications ............................................................................................................................. 19 table 4-7. 60x bus input timing specifications .................................................................................................................... 21 table 4-8. 60x bus output ac timing specifications ......................................................................................................... 22 table 4-9. jtag ac timing specifications (independent of sysclk) ........................................................ 25 table 5-1. signal listing for the 256 pbga package ............................................................................. ...... 31 table 5-2. ppc750 signals not supported in the 750cxr .......................................................................... .32 table 5-3. signal locations .................................................................................................... ...................... 33 table 5-4. voltage and ground assignments ...................................................................................... ......... 34 table 6-1. powerpc 750cxr microprocessor pll configuration ................................................................. 35 table 6-2. driver impedance characteristics .................................................................................... ........... 38 table 6-3. input-output usage .................................................................................................. ................... 39
data sheet powerpc ? 750cxr risc microprocessor page 6 of 43 sw_ds_750cxrlot.fm february 28, 2005
data sheet powerpc ? 750cxr risc microprocessor sw_ds_750cxrlof.fm february 28, 2005 page 7 of 43 figures figure 1-1. ibm part number key ................................................................................................ ................ 11 figure 2-1. powerpc 750cxr block diagram ....................................................................................... ....... 13 figure 4-1. sysclk input timing diagram ........................................................................................ .......... 19 figure 4-2. linear sweep modulation profile .................................................................................... ........... 20 figure 4-3. input timing diagram ............................................................................................... .................. 21 figure 4-4. mode select input timing diagram ................................................................................... ......... 22 figure 4-5. output valid timing definition ..................................................................................... ............... 23 figure 4-6. output timing diagram for powerpc 750cxr ........................................................................... 24 figure 4-7. jtag clock input timing diagram .................................................................................... ......... 25 figure 4-8. trst timing diagram ............................................................................................................... 26 figure 4-9. boundary-scan timing diagram ....................................................................................... ......... 26 figure 4-10. test access port timing diagram ................................................................................... ......... 26 figure 5-1. pinout of the 256 pbga package as viewed from solder ball side .......................................... 28 figure 5-2. side profile view of pbga .......................................................................................... ............... 29 figure 5-3. side profile view showing exposed cavity ........................................................................... .... 29 figure 5-4. powerpc 750cxr microprocessor ball placement .................................................................... 30 figure 6-1. pll power supply filter circuit .................................................................................... ............. 36 figure 6-2. driver impedance measurement ....................................................................................... ......... 37 figure 6-3. ibm riscwatch jtag to hreset , trst , and sreset signal connector ............................ 41 figure 6-4. pbga package thermal model ......................................................................................... ........ 42
data sheet powerpc ? 750cxr risc microprocessor page 8 of 43 sw_ds_750cxrlof.fm february 28, 2005
data sheet powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 general information page 9 of 43 1. general information the powerpc ? 750cxr risc microprocessor is an implementation of the powerpc family of reduced instruction set computer (risc) microprocessors. the information in this document is specific to revision dd 4.0 of the 750cxr and may not apply to subsequent revisions. 1.1 features this section summarizes the major features of the powerpc 750cxr implementation of the powerpc architecture. ? branch processing unit - four instructions fetched per clock - one branch processed per cycle (plus resolving 2 speculations) - up to 1 speculative stream in execution, 1 additional speculative stream in fetch - 512-entry branch history table (bht) for dynamic prediction - 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots dispatch unit - full hardware detection of dependencies (resolved in the execution units) - dispatch two instructions to six independent units (system, branch, load/store, fixed- point unit 1, fixed-point unit 2, or floating- point) - 4-stage pipeline: fetch, dispatch, execute, and complete - serialization control (predispatch, postdispatch, execution, serialization) fixed-point units - fixed-point unit 1 (fxu1); multiply, divide, shift, rotate, arithmetic, logical - fixed-point unit 2 (fxu2); shift, rotate, arithmetic, logical - single-cycle arithmetic, shift, rotate, logical - multiply and divide support (multi-cycle) - early out multiply - thirty-two, 32-bit general purpose registers - secondary fxu executes integer add/compare instructions decode - register file access - forwarding control - partial instruction decode load/store unit - one cycle load or store cache access (byte, half-word, word, double-word) - effective address generation - hits under misses (one outstanding miss) - single-cycle misaligned access within double word boundary - alignment, zero padding, sign extend for integer register file - floating-point internal format conversion (alignment, normalization) - sequencing for load/store multiples and string operations - store gathering - cache and tlb instructions - big and little-endian byte addressing supported - misaligned little-endian support in hardware floating-point unit - support for ieee-754 standard single and double-precision floating-point arithmetic - optimized for single-precision multiply/add - thirty-two, 64-bit floating point registers - enhanced reciprocal estimates - 3-cycle latency, 1-cycle throughput, single- precision multiply-add - 3-cycle latency, 1-cycle throughput, double- precision add - 4-cycle latency, 2-cycle throughput, double- precision multiply-add
data sheet powerpc ? 750cxr risc microprocessor preliminary general information page 10 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 floating-point unit (continued) - hardware support for divide - hardware support for denormalized numbers - time deterministic non-ieee mode system unit - executes cr logical instructions and miscellaneous system instructions - special register transfer instructions l1 cache structure - 32kb, 32-byte line, 8-way set associative instruction cache - 32kb, 32-byte line, 8-way set associative data cache - single-cycle cache access - pseudo-lru replacement - copy-back or write-through data cache (on a page per page basis) - 3-state (mei) memory coherency - hardware support for data coherency - non-blocking instruction and data cache (one outstanding miss under hits) - no snooping of instruction cache memory management unit - 128-entry, 2-way set associative instruction tlb - 128-entry, 2-way set associative data tlb - hardware reload for tlbs - 4 instruction bats and 4 data bats - virtual memory support for up to 4 pb (2 52 ) virtual memory - real memory support for up to 4 gb (2 32 ) of physical memory - support for big/little-endian addressing level 2 (l2) cache - internal l2 cache controller and 4kb-entry tags; 256kb data srams - copy-back or write-through data cache on a page basis, or for all l2 - 64-byte sectored line size - l2 frequency at core speed - on-board ecc bus interface - compatible with 60x processor interface (some pin functions removed, see table 5-2 on page 31) - 32-bit address bus - 64-bit data bus (also supports 32-bit mode) - core-to-bus frequency multipliers of 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, supported power - 6w typical @ 400mhz testability - lssd scan design - powerful diagnostic and test interface through common on-chip processor (cop) and ieee 1149.1 (jtag) interface
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 general information page 11 of 43 1.2 special design level considerations/features the powerpc 750cxr supports several unique features including those listed below. section 6.7 ?operational and design considerations,? on page 41 provides a more detailed explanation of these features. provides a 64- or 32-bit data bus mode (per setup of qack pin). supports 1.8v and 2.5v i/o signals. uses a reduced pin list from earlier powerpc 750 designs (see table 5-2 on page 31). data bus write only (dbwo ) shares a common pin with l2_testclk. chkstp_out shares a common pin with clk_out. 1.3 ordering information for available devices, contact your local ibm sales office. figure 1-1 provides the ibm part numbering nomenclature for the powerpc 750cxr. figure 1-1. ibm part number key ibm25ppc750cxrkq0124t powerpc 750 family member enhanced process test conditions shipping container reliability grade performance sort package type design revision level design revision level k = 4.0 package type q = lead free plastic/laminate ball grid array performance sort 01 = 300mhz, 333mhz w/o l2 03 = 300mhz, 333mhz 10 = 366 mhz 20 = 400mhz 40 = 466 mhz 50 = 500mhz 55 = 533mhz test conditions 2 = +1.8v to +1.9v @ 95 c for < 500mhz, +1.85v to +1.95v @ 95 c for 500 mhz and 533mhz reliability grade 4 = grade 4 shipping container t = tray
data sheet powerpc ? 750cxr risc microprocessor preliminary general information page 12 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 1.4 processor version register (pvr) the powerpc 750cxr has the following pvr values for the respective design revision levels. table 1-1. process version register (pvr) design revision level pvr dd4.0 00083410
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 overview page 13 of 43 2. overview the powerpc 750cxr is targeted for high performance, low power systems and a 60x bus. the powerpc 750cxr also includes an internal 256kb l2 cache with on-board error correction circuitry (ecc). 2.1 powerpc 750cxr block diagram figure 2-1 shows a block diagram of the powerpc 750cxr. figure 2-1. powerpc 750cxr block diagram gprs lsu fpu instruction fetch system completion rename buffers unit 32kb i-cache bht / biu 60x l2 cache fxu2 dispatch branch unit btic control unit fprs rename buffers 256kb 32kb d-cache l2 tags fxu1
data sheet powerpc ? 750cxr risc microprocessor preliminary general parameters page 14 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 3. general parameters table 3-1 provides a summary of the general parameters of the powerpc 750cxr. table 3-1. general parameters item description technology 0.18 m cmos copper technology, six-layer metallization die size 42.7mm 2 transistor count 20 million (including l2 cache) logic design fully static package surface mount 256-lead plastic ball grid array (pbga), lead free 27mm x 27mm core power supply 1.85v for <500mhz, 1.9v for 500mhz and 533mhz i/o power supply +1.8v 5% +2.5v 5%
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 electrical and thermal characteristics page 15 of 43 4. electrical and thermal characteristics this section provides both ac and dc electrical specifications, and thermal characteristics for the powerpc 750cxr. 4.1 dc electrical characteristics the tables in this section describe the powerpc 750cxr?s dc electrical characteristics. table 4-1 provides the absolute maximum ratings. table 4-2 provides the recommended operating conditions for the powerpc 750cxr. table 4-1. absolute maximum ratings characteristic symbol value (bvsel = 0) value (bvsel = 1) unit core supply voltage v dd -0.3 to +2.0 -0.3 to +2.00 v pll supply voltage av dd -0.3 to +2.0 -0.3 to +2.00 v 60x bus supply voltage ov dd -0.3 to +2.0 -0.3 to +2.75 v input voltage v in -0.3 to +2.0 -0.3 to +2.75 v storage temperature range t stg -55 to +150 -55 to +150 c notes: 1. functional and tested operating conditions are given in table 4-2 on page 15. absolute maximum ratings are stress ratings only, and functional opera- tion at the maximums is not guaranteed. stresses beyond those listed above may affect device reliability or cause permanent dam age to the device. 2. caution: v in must not exceed ov dd by more than 0.6v at any time, including during power-on reset. this is a dc specification only. v in overshoot tran- sients up to ov dd +0.8v,and undershoots down to gnd-0.8v (both measured with the 750cxr in the circuit) are allowed for up to 5ns or 1/3 bus cloc k cycle, whichever is less. 3. caution: ov dd must not exceed v dd /av dd by more than 2.0v, except for up to 20 ms during power on/off reset. 4. caution: v dd /av dd must not exceed ov dd by more than 1.2v, except for up to 20 ms during power up/down. 5. caution: av dd must not exceed v dd by more than 1.2v, except for up to 20ms during power up/down reset. table 4-2. recommended operating conditions characteristic 1 symbol value unit core supply voltage < 500mhz v dd +1.8 to +1.9 v core supply voltage @ 500 mhz and 533 mhz v dd +1.85 to +1.95 v pll supply voltage av dd +1.8 to +1.95 v 60x bus supply voltage (1.8v mode) ov dd +1.8 to +1.9 v 60x bus supply voltage (2.5v mode) ov dd +2.375 to +2.625 v input voltage v in gnd to ov dd v die-junction temperature (grade 4) t j 0 to +95 c note: these are recommended and tested operating conditions. proper device operation outside of t hese conditions is not guaranteed. 1. see performance sort in section 1.3 on page 11.
data sheet powerpc ? 750cxr risc microprocessor preliminary electrical and thermal characteristics page 16 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 table 4-3 provides the package thermal characteristics for the powerpc 750cxr. table 4-4 provides dc electrical characteristics for the powerpc 750cxr. table 4-3. package thermal characteristics characteristic symbol value unit pbga package thermal resistance, junction to ambient, thermal resistance, convection only 1 ja 15.9 c/w pbga package thermal resistance, junction-to-ambient thermal resistance, 100 linear ft. per minute ja 13.9 c/w pbga package thermal resistance, junction-to-board thermal resistance jb 7.4 c/w pbga package thermal resistance, junction-to-case thermal resistance jc 0.7 c/w note: 1. assumes that the package is soldered to a 2s2p board. table 4-4. dc electrical specifications see table 4-2 on page 15 for recommended operating conditions. characteristic symbol voltage unit notes min max input high voltage (all inputs except sysclk) v ih (1.8v) +1.3 +1.9 v 2, 4 v ih(2.5v) +1.9 +2.625 v 2 input low voltage (all inputs except sysclk) v il(1.8v) gnd +0.66 v 4 v il(2.5v) gnd +0.7 v sysclk input high voltage cv ih(1.8v) +1.3 +1.9 v cv ih(2.5v) +1.95 +2.625 v sysclk input low voltage cv il(1.8v/2.5v) gnd +0.4 v input leakage current, v in = ov dd = 2.5v i in ?20 a3 input leakage current, v in = ov dd = 1.8v i in ?20 a3 hi-z (off state) leakage current, v in = ov dd = 2.5v i tsi ?20 a3 hi-z (off state) leakage current, v in = ov dd = 1.8v i tsi ?20 a3 output high voltage, i oh = ?4ma v oh(1.8v) +1.4 ? v v oh(2.5v) +2.1 ? v output low voltage, i ol = 4ma v ol(1.8v, 2.5v) ?+0.4v capacitance, v in =0 v, f = 1mhz c in ?+5.0pf 1 notes: 1. capacitance values are guaranteed by design and characterization, and are not tested. 2. maximum input high voltage for short duration (not continuous operation). 3. additional input current may be attributed to the level protection keeper lock circuity. for details, see section 6.7 on page 41. 4. v ih and v il minimum levels are set as a percentage of v dd . v ih is 65% and v il is 35% respectively.
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 electrical and thermal characteristics page 17 of 43 table 4-5 provides the power consumption for the powerpc 750cxr. table 4-5. power consumption see table 4-2 on page 15 for recommended operating conditions. power mode v dd t j representative processor frequency unit notes 300/333 mhz (no l2) 300/333 mhz (with l2) 366mhz 400mhz 466 mhz 500mhz 533mhz full-on mode maximum 1.95v 95c 9.2 9.8 w 1, 2, 4 1.9v 95c 6.8 6.8 7.0 7.5 8.2 w typical 1.9v 65c 7.3 7.8 w 1, 3, 4 1.85v 65c 5.2 5.2 5.6 6.0 6.7 w doze mode maximum 1.95v 95c 5.9 6.4 w 1, 2, 4 1.9v 95c 4.4 4.4 4.8 5.05 5.4 w typical 1.9v 65c 4.3 4.8 w 1, 3, 4 1.85v 65c 3.1 3.1 3.4 3.6 3.9 w nap mode maximum 1.95v 95c 3.05 3.3 w 1, 2, 4 1.9v 95c 2.5 2.5 2.7 2.85 2.85 w typical 1.9v 65c 1.65 1.65 w 1, 3, 4 1.85v 65c 1.5 1.5 1.5 1.5 1.55 w sleep mode maximum 1.95v 95c 3.0 32 w 1, 2, 4 1.9v 95c 2.5 2.5 26 2.8 2.85 w typical 1.9v 50c 1.22 1.28 w 1, 3, 4 1.85v 50c 1.08 1.08 1.1 1.12 1.12 w notes: 1. these values apply for all valid 60x buses. the values do not include i/o supply power (ov dd ) or pll/dll supply power (av dd ). ov dd power is system dependent, but is typically < 5% of v dd power. av dd current is less tha 25ma. 2. maximum power is specified for a mix of parts (both fast and slow process) running rc5 at the indicated core voltage, junctio n temperature, and core frequency. 3. typical power is specified for a mix of parts (both fast and slow process) running rc5 at the indicated core voltage, junctio n temperature, and core frequency. 4. guaranteed by design and characterization, and is not tested.
data sheet powerpc ? 750cxr risc microprocessor preliminary electrical and thermal characteristics page 18 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 4.2 ac electrical characteristics this section provides the ac electrical characteristics for the powerpc 750cxr. after fabrication, parts are sorted by maximum processor core frequency as shown in the section 4.2.1 on page 18, and tested for conformance to the ac specifications for that frequency. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg(0-3) signals. 4.2.1 clock ac specifications table 4-6 provides the clock ac timing specifications as defined in figure 4-1. table 4-6. clock ac timing specifications 1,6 see table 4-2 on page 15, for recommended operating conditions. num characteristic value unit notes min max processor frequency 300 533 mhz sysclk frequency 66 133 mhz 1 1 sysclk cycle time 7.5 15 ns 2, 3 sysclk rise and fall time (slew rate) 1.0 4.0 v/ns 2, 3 4 sysclk duty cycle measured at 0.8v 25 75 % 3 sysclk jitter ? 150 ps 4, 3 internal pll relock time ? 100 s5 notes: 1. caution: the sysclk frequency and the pll_cfg[0:3] settings must be chosen such that the resulting sysclk (bus) frequency and cpu (core) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:3] signal description in section 6.1 ?pll configuration,? on page 34 for valid pll_cfg[0:3] settings. 2. rise and fall times for the sysclk input are measured from +0.4 to +1.2 v. 3. timing is guaranteed by design and characterization, and is not tested. 4. the total input jitter (short term and long term combined) must be under 150ps. contact ibm for use with spread-spectrum clocks or clocks with jitter in excess of 150ps. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. figure 4-1. sysclk input timing diagram vm cv il cv ih 1 2 4 3 4 sysclk vm - midpoint voltage (+0.85v)
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 electrical and thermal characteristics page 19 of 43 4.3 spread spectrum cl ock generator (sscg) when designing with an sscg, there are a number of issues that must be taken into account. an sscg creates a controlled amount of long-term jitter. in order for a receiving pll in the 750cxr to function correctly in this environment, it must be able to accurately track the sscg clock jitter. the accuracy with which the 750cxr pll can track the sscg is referred to as tracking skew. when performing system timing analysis, the tracking skew must be added to or subtracted from the i/o timing specifications, because the skew appears as a static phase error between the internal pll and the sscg clock. to minimize the impact on i/o timing, the following sscg configuration is recommended: down-spread mode 1% of the maximum frequency modulation frequency of 30 khz linear sweep modulation or a modulation profile (hershey kiss ? ) as shown in figure 4-2. in this configuration, the tracking skew is less than 100ps. figure 4-2. linear sweep modulation profile 0% -1% 0 s 33.3 s down spread time frequency
data sheet powerpc ? 750cxr risc microprocessor preliminary electrical and thermal characteristics page 20 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 4.4 60x bus input ac specifications table 4-7 provides the 60x bus input ac timing specifications for the powerpc 750cxr as defined in figure 4-3 and figure 4-4. figure 4-3 provides the input timing diagram for the powerpc 750cxr. table 4-7. 60x bus input timing specifications 1,6 see table 4-2 on page 15 for operating conditions. num characteristic 1.8v mode 2.5v mode unit notes min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 1.15 ? 1.25 ? ns 2 10b all other inputs valid to sysclk (input setup) 1.15 ? 1.25 ? ns 3 10c mode select input setup to hreset (qack )8?8?t sysclk 4, 5, 7 10d ts to sysclk (input setup) 1.35 ? 1.4 ? ns ? 10e dbwo to sysclk (input setup) 1.5 ? 1.6 ? ns ? 11a sysclk to inputs invalid (input hold) 0.65 ? 0.3 ? ns 2 11b hreset to mode select input hold (qack )0?0?ns4, 7 notes: 1. input specifications are measured from the midpoint voltage of the signal in question to the midpoint voltage of the rising e dge of the input sysclk. input and output timings are measured at the pin (see figure 4-3). the midpoint voltage used for all pins is 0.85v for 1.8v mode and 1.2v for 2.5v mode. 2. address/data transfer attribute inputs are composed of all bidirectional and input signals except those listed in note 3. 3. all other signal inputs are composed of the following: ta , qack , and artry . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 4-4 on page 21). 5. t sysclk , is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the pe riod of sysclk to compute the actual time duration (in ns) of the parameter in question. 6. these values are guaranteed by design and characterization, and are not tested. 7. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time during the power-on reset sequence. figure 4-3. input timing diagram vm sysclk all inputs vm = midpoint voltage (+0.85v for 1.8v mode or 1.2v for 2.5v mode) 10b 10a 11a vm vm 10d 10e
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 electrical and thermal characteristics page 21 of 43 figure 4-4 provides the mode select input timing diagram for the powerpc 750cxr. 4.5 60x bus output ac specifications table 4-8 provides the 60x bus output ac timing specifications for the powerpc 750cxr as defined in figure 4-7 on page 24. figure 4-4. mode select input timing diagram table 4-8. 60x bus output ac timing specifications 1,4,6 see table 4-2 on page 15 for operating conditions. num characteristic 1.8v mode 2.5v mode unit notes min. max. min. max. 12 sysclk to output driven (output enable time) 0.3 0.3 ns 13 sysclk to output valid ? 2.31 ? 2.2 ns 14 sysclk to output invalid (output hold) 0.4 0.4 ns 2 15 sysclk to output high impedance (all signals except artry ) ?2.5?2.5ns 16 sysclk to artry high impedance before precharge ? 3.0 ? 3.0 ns 17 sysclk to artry precharge enable 0.2t sysclk +1.0 0.2t sysclk +1.0 ns 2, 3, 5 18 maximum delay to artry precharge 1 1 t sysclk 3, 5 19 sysclk to artry high impedance after precharge 2 2 t sysclk 3, 5 notes: 1. all output specifications are measured from the midpoint voltage of the rising edge of sysclk to the midpoint voltage of the signal in question defined in figure 4-5. both input and output timings are measured at the pin. timings are determined by design. the midpoint vol tage used for all pins is 0.85v for 1.8v mode and 1.2v for 2.5v mode. 2. this minimum parameter assumes cl = 0pf. 3. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 4. output signal transitions are defined in figure 4-5. 5. nominal precharge width for artry is 1.0 t sysclk . 6. guaranteed by design and characterization, and not tested. v ih v ih = +1.3 v mode pins 10c 11b hreset 10c 11b
data sheet powerpc ? 750cxr risc microprocessor preliminary electrical and thermal characteristics page 22 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 figure 4-5. output valid timing definition 65 ? line output driver sysclk positive output transition negative output transition 1/4 ov dd 3/4 ov dd output transition defined between sysclk @ +0.85 v and the respective transition level. ( note: the timing definition uses an infinitely long transmission line model.) vmeasure
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 electrical and thermal characteristics page 23 of 43 figure 4-6. output timing diagram for powerpc 750cxr sysclk all outputs (except ts , artry ) ts artry 12 13 13 14 15 15 vm vm 14 vm 13 18 16 19 17 vmeasure vmeasure vmeasure low level hi-z high level vmeasure is defined with reference to figure 4-5 as 1/4 of the transition of ov dd .
data sheet powerpc ? 750cxr risc microprocessor preliminary electrical and thermal characteristics page 24 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 4.5.1 ieee 1149.1 ac timing specifications table 4-9 provides the ieee 1149.1 (jtag) ac timing specifications as defined in figure 4-7, figure 4-8, figure 4-9, and figure 4-10. the five jtag signals are; tdi, tdo, tms, tck, and trst . figure 4-7 provides the jtag clock input timing diagram. table 4-9. jtag ac timing specifications (independent of sysclk) see table 4-2 on page 15 for operating conditions. num characteristic min max unit notes tck frequency of operation 0 20 mhz 1 tck cycle time 50 ? ns 2 tck clock pulse width measured at +1.1v 15 ? ns 3 tck rise and fall times 0 2 ns 4 4 specification obsolete, intentionally omitted 5trst assert time 25 ? ns 1 6 boundary-scan input data setup time 0 ? ns 2 7 boundary-scan input data hold time 13 ? ns 2 8 tck to output data valid ? 8 ns 3, 5 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 ? ns 11 tms, tdi data hold time 15 ? ns 12 tck to tdo data valid 2.5 12 ns 5 13 tck to tdo high impedance 3 9 ns 4 14 tck to output data invalid (output hold) 0 ? ns notes: 1. trst is an asynchronous level sensitive signal. guaranteed by design. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by characterization and not tested. 5. minimum specification guaranteed by characterization and not tested. figure 4-7. jtag clock input timing diagram 1 2 2 3 3 vm = midpoint voltage vm tck vm vm
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 electrical and thermal characteristics page 25 of 43 figure 4-8 provides the trst timing diagram. figure 4-9 provides the boundary-scan timing diagram. figure 4-10 provides the test access port timing diagram. figure 4-8. trst timing diagram figure 4-9. boundary-scan timing diagram figure 4-10. test access port timing diagram 5 trst 9 6 7 8 9 tck data inputs data outputs data outputs input data valid output data valid 12 10 11 tck tdi, tms tdo tdo input data (valid) output data (valid) tdo 13 14 output data (invalid)
data sheet powerpc ? 750cxr risc microprocessor preliminary powerpc 750cxr dimension and physical signal assignments page 26 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 5. powerpc 750cxr dimension and physical signal assignments ibm offers a plastic ball grid array, pbga, which supports 256 balls as the powerpc 750cxr lead free package. this package is jedec msl-3 and should be handled accordingly. the following sections contain several views of the package, pin information, and a pin listing. figure description figure number and page shows the pinout of the 256 pbga package as viewed from the solder ball surface. figure 5-1 on page 27 shows a side profile of the 256 pbga package including the height from the top of the cop- per heat spreader to the bottom of the solder balls. figure 5-2 on page 28 provides a more detailed side profile in cluding the encapsulant (glob) referenced. figure 5-3 on page 28
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 powerpc 750cxr dimension and physical signal assignments page 27 of 43 . figure 5-1. pinout of the 256 pbga package as viewed from solder ball side abcdefghjklmnprt 01 02 04 05 06 07 08 09 10 11 12 13 15 16 17 18 19 uvw 20 y 03 14 d d1 e e1 dimension nominal length (mm) c 15.1 max d 27.00 d1 24.13 e 27.00 e1 24.13 1.27 c
data sheet powerpc ? 750cxr risc microprocessor preliminary powerpc 750cxr dimension and physical signal assignments page 28 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 figure 5-2. side profile view of pbga figure 5-3. side profile view showing exposed cavity item description length (mm) height (mm) a cu heat spreader 27 0.356 nominal b laminate including plating 27 0.585 +/-0.076 c solder ball n/a 0.58 +/- 0.08 d chip cavity 15.1 max 0.47 max e minimum glop to solder ball height n/a 0.03 f cu heat spreader, laminate, bond pads, and plating n/a 0.955 +/-0.1 note: dimension a consists of the entire pac kage with solder balls before reflow. dimension total package height (mm) a 1.539 +/-0.127 a a b c d e nickel plated surface bond pads and solder mask f
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 powerpc 750cxr dimension and physical signal assignments page 29 of 43 figure 5-4. powerpc 750cxr microprocessor ball placement 1 2 3 4 5 6 7 8 9 1011121314151617181920 a g g dh3 g dh9 dh11 dh13 dh15 dh16 dh19 dh20 dh23 dh24 dh26 dh28 dh30 g a4 g g b g g vdd dh4 dh6 dh8 dh12 g dh18 g g dh21 g dh27 dh31 a1 a3 vdd g g c dh2 vdd g vdd ovdd dh7 dh10 dh14 dh17 g g dh22 dh25 dh29 a0 ovdd vdd g vdd a5 d ovdd dh1 vdd g vdd dh5 ovdd vdd ovdd vdd vdd ovdd vdd ovdd a2 vdd g vdd a6 g e hreset dh0 dbwo 1 vdd vdd ovdd a8 a11 f pllcfg0 lssd_mode mcp l1_tstclk a7 a9 a10 a13 g pllcfg2 pllcfg1 sysclk ovdd ovdd a12 a14 a15 h bvsel pllcfg3 avdd vdd vdd tt_0 g tt_1 j gint ckstp_in ovdd ovdd tt_3 ts tt_2 k sreset qack gvdd vdd g g tt_4 l qreq ggvdd vdd g g tsiz0 m dbg tea artry ovdd ovdd tsiz2 tsiz1 ta n br gtdovdd vdd aack gtbst p bg ckstp_out tdi ovdd ovdd a19 a17 a16 r wt gbl tms trst a24 a22 a21 a18 t dl31 ci tck vdd vdd ovdd a23 a20 u ovdd dl30 vdd g vdd dl26 ovdd vdd ovdd vdd vdd ovdd vdd ovdd a29 vdd g vdd a25 g v dl29 vdd g vdd ovdd dl24 dl21 dl17 dl14 g g dl9 dl6 dl2 a31 ovdd vdd g vdd a26 w g g vdd dl27 dl25 dl23 dl19 g dl13 g g dl10 g dl4 dl0 a30 a28 vdd g g y g g dl28 g dl22 dl20 dl18 dl16 dl15 dl12 dl11 dl8 dl7 dl5 dl3 dl1 g a27 g g note: this view is looking down from above the powerpc 750cxr placed and soldered on the system board. 1. dbwo multiplexed with l2_tstclk function, see section 6.7.4 on page 42 for details.
data sheet powerpc ? 750cxr risc microprocessor preliminary powerpc 750cxr dimension and physical signal assignments page 30 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 table 5-1. signal listing for the 256 pbga package signal name pin count active i/o notes a0?a31 32 high i/o aack 1 low input artry 1 low i/o bg 1 low input br 1 low output ci 1 low output ckstp_in 1 low input ckstp_out 2 1 low output dbg 1 low input dh0-dh31 32 high i/o dl0-dl31 32 high i/o gbl 1 low i/o hreset 1 low input int 1 low input l1_tstclk 1 1 high input dbwo /l2_tstclk 1,2,3 1 high input lssd_mode 1 1 low input mcp 1 low input pll_cfg[0-3] 4 high input qack 2 1 low input optional: 64/32-bit data bus mode select. this function will be set when hreset transitions (low to high). qack : low = 64-bit mode, high = 32-bit mode. qreq 1 low output sreset 1 low input sysclk 1 ? input ta 1 low input tbst 1 low i/o tck 1 high input tdi 1 high input tdo 1 high output tea 1 low input tms 1 high input trst 1 low input notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. the ckstp_out signal in test mode allows viewing the powerpc 750cxr internal clocks. the qack signal allows selection of 32-bit mode.(see the powerpc 750cxr user?s manual for more information.) 3. l2-tstclk in normal mode is dbwo , for details, see section 6.7.4 on page 42.
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 powerpc 750cxr dimension and physical signal assignments page 31 of 43 ts 1 low i/o tsiz0?tsiz2 3 high output tt0?tt4 5 high i/o wt 1 low output bvsel 1 high input pin set low = +1.8 v, pin set high = +2.5 v av dd 1 supply for pll ov dd 24 supply for receiver/drivers v dd 40 supply for core ground 53 common ground table 5-2. ppc750 signals not supported in the 750cxr signal name pin count active i/o abb 1 low i/o dbb 1 low i/o dbdis 1 low input rsrv 1 low output smi 1 low input tben 1 high input voltdet 1 high output ap0?3 4 high i/o dp0?7 8 high i/o drtry 1 low input tlbisync 1 low input table 5-1. signal listing for the 256 pbga package (continued) signal name pin count active i/o notes notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. the ckstp_out signal in test mode allows viewing the powerpc 750cxr internal clocks. the qack signal allows selection of 32-bit mode.(see the powerpc 750cxr user?s manual for more information.) 3. l2-tstclk in normal mode is dbwo , for details, see section 6.7.4 on page 42.
data sheet powerpc ? 750cxr risc microprocessor preliminary powerpc 750cxr dimension and physical signal assignments page 32 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 table 5-3. signal locations signal ball location signal ball location signal ball location signal ball location a0 c15 dh0 e2 dl0 w15 aack n18 a1 b16 dh1 d2 dl1 y16 artry m3 a2 d15 dh2 c1 dl2 v14 bg p1 a3 b17 dh3 a3 dl3 y15 br n1 a4 a18 dh4 b4 dl4 w14 bvsel h1 a5 c20 dh5 d6 dl5 y14 ci t2 a6 d19 dh6 b5 dl6 v13 ckstp_in j3 a7 f17 dh7 c6 dl7 y13 ckstp_out p2 a8 e19 dh8 b6 dl8 y12 dbg m1 a9 f18 dh9 a5 dl9 v12 gbl r2 a10 f19 dh10 c7 dl10 w12 hreset e1 a11 e20 dh11 a6 dl11 y11 int j2 a12 g18 dh12 b7 dl12 y10 l1_tstclk f4 a13 f20 dh13 a7 dl13 w9 dbwo /l2_tstclk 1 e3 a14 g19 dh14 c8 dl14 v9 lssd_mode f2 a15 g20 dh15 a8 dl15 y9 mcp f3 a16 p20 dh16 a9 dl16 y8 pll_cfg0 f1 a17 p19 dh17 c9 dl17 v8 pll_cfg1 g2 a18 r20 dh18 b9 dl18 y7 pll_cfg2 g1 a19 p18 dh19 a10 dl19 w7 pll_cfg3 h2 a20 t20 dh20 a11 dl20 y6 qack (also used for 64/32-bit db select.) k2 a21 r19 dh21 b12 dl21 v7 qreq l1 a22 r18 dh22 c12 dl22 y5 sreset k1 a23 t19 dh23 a12 dl23 w6 sysclk g3 a24 r17 dh24 a13 dl24 v6 ta m20 a25 u19 dh25 c13 dl25 w5 tbst n20 a26 v20 dh26 a14 dl26 u6 tck t3 a27 y18 dh27 b14 dl27 w4 tdi p3 a28 w17 dh28 a15 dl28 y3 tdo n3 a29 u15 dh29 c14 dl29 v1 tea m2 a30 w16 dh30 a16 dl30 u2 tms r3 a31 v15 dh31 b15 dl31 t1 trst r4 ts j19 tsiz0 l20 tsiz1 m19 tsiz2 m18 tt0 h18 tt1 h20 tt2 j20 tt3 j18 tt4 k20 wt r1 note: 1. see section 6.7.4 on page 42 for a detailed discussion.
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 powerpc 750cxr dimension and physical signal assignments page 33 of 43 table 5-4. voltage and ground assignments av dd ov dd v dd v dd gnd gnd h3 m4 b3 l4 a1 l3 m17 b18 l17 a2 l18 p4 c2 n4 a4 l19 p17 c4 n17 a17 n2 t18 c17 t4 a19 n19 u1 c19 t17 a20 u4 u7 d3 u3 b1 u17 u9 d5 u5 b2 u20 u12 d8 u8 b8 v3 u14 d10 u10 b10 v10 v5 d11 u11 b11 v11 v16 d13 u13 b13 v18 c5 d16 u16 b19 w1 c16 d18 u18 b20 w2 d1 e4 v2 c3 w8 d7 e17 v4 c10 w10 d9 h4 v17 c11 w11 d12 h17 v19 c18 w13 d14 k4 w3 d4 w19 e18 k17 w18 d17 w20 g4 d20 y1 g17 h19 y2 j4 j1 y4 j17 k3 y17 k18 y19 k19 y20 l2
data sheet powerpc ? 750cxr risc microprocessor preliminary system design information page 34 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 6. system design information this section provides electrical and thermal design recommendations for successful application of the powerpc 750cxr. 6.1 pll configuration pll-cfg (table 6-1) must be set so that both sysclk and the core frequency are within the clock ac timing specifications shown in table 4-6 on page 18. in addition, the core frequency must not exceed the limit specified in the part number, and the system must meet the required specifications. 6.2 pll power supply filtering the av dd power signal is provided on the powerpc 750cxr to provide power to the clock generation phase- locked loop. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered using a circuit similar to the one shown in figure 6-1. the circuit should be placed as close as table 6-1. powerpc 750cxr microprocessor pll configuration pll_cfg (0:3) processor to bus frequency ratio (r) bin dec 0000 0 2.5x 0001 1 7.5x 1 0010 2 7x 0011 3 pll bypass 2 0100 4 2x 1 0101 5 6.5x 0110 6 9x 1 10x 1 0111 7 4.5x 1000 8 3x 1001 9 5.5x 1010 10 4x 1011 11 5x 1100 12 8x 1 1101 13 6x 1110 14 3.5x 1111 15 off 3 notes: 1. the 2x,7.5x, 8x 9x, and 10x processor to bus ratios are currently not supported. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode oper- ation. this mode is intended for factory use only. note: the ac timing specifications given in the document do not apply in pll-bypass mode. 3. in clock - off mode, no clocking occurs inside the powerpc 750cxr regardless of the sysclk input.
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 system design information page 35 of 43 possible to the av dd pin to ensure it filters out as much noise as possible. the referenced ferrite bead, fb, shown in figure 6-1 should supply an impedance of approximately 30 ? in the 100mhz region (murata blm21p300s or similar). 6.3 decoupling recommendations due to the powerpc 750cxr?s feature large address and data buses, and high operating frequencies, the powerpc 750cxr can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the powerpc 750cxr system, and the powerpc 750cxr itself requires a clean, tightly regulated source of power. therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low esr (effective series resistance) rating at each vdd and ovdd pin of the powerpc 750cxr. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should range in value from 220pf to 10 f to provide both high and low-frequency filtering, and should be placed as close as possible to their associated vdd or ovdd pins. suggested values for the vdd pins: 220pf (ceramic x7r), 0.01 f (ceramic x7r), and 0.1 f (ceramic x7r). suggested values for the ovdd pins: 0.01 f (ceramic x7r), 0.1 f (ceramic x7r), and 10 f (tantalum). only smt (surface-mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ovdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors: 100 f (avx tps tantalum) or 330 f (avx tps tantalum). figure 6-1. pll power supply filter circuit v dd av dd 2 ? 10 f 0.1 f gnd fb
data sheet powerpc ? 750cxr risc microprocessor preliminary system design information page 36 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 6.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd pins of the powerpc 750cxr. 6.5 output buffer dc impedance the powerpc 750cxr 60x drivers were characterized over various process, voltage, and temperature conditions. to measure z 0 , an external resistor is connected to the chip pad, either to ov dd or gnd. then the value of the resistor is varied until the pad voltage is ov dd /2; see figure 6-2 below. the output impedance is actually the average of two resistances: the resistance of the pull-up and the resistance of pull-down devices. when data is held low, sw2 is closed (sw1 is open), and r n is trimmed until pad = ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r p is trimmed until pad = ov dd /2. r p then becomes the resistance of the pull- up devices. with a properly designed driver r p and r n are close to each other in value, then z 0 = (r p + r n )/2. figure 6-2. driver impedance measurement data ov dd r n sw2 sw1 pad r p gnd
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 system design information page 37 of 43 table 6-2 on page 37 summarizes the impedance a board designer would design to for a typical process. 6.5.1 input-output usage table 6-3 provides details on the input-output usage of the powerpc 750cxr signals. the column titled usage group refers to the general functional category of the signal. in the powerpc 750cxr, certain input-output signals have pull-ups and pull-downs, which may or may not be enabled. the column titled i/o with internal resistors defines which signals have these pull-ups or pull- downs, and their active or inactive state. the column titled ?level protect? defines which signals have the designated function added to their i/o cell. for more information, see section 6.7.1 ?level protection,? on page 41. table 6-2. driver impedance characteristics process 60x impedance ( ? )v dd , ov dd (v) temperature ( c) worst 65 1.8, 1.8 95 typical 50 1.85, 1.85 65 best 40 1.90, 1.90 0 worst 65 1.8, 2.38 95 typical 50 1.85, 2.5 65 best 40 1.90, 2.62 0
data sheet powerpc ? 750cxr risc microprocessor system design information page 38 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 table 6-3. input-output usage powerpc 750cxr signal name active level input/ output usage group i/o with internal resistors level protect required external resistor comments a0-31 n/a bidi address bus keeper see notes 1, 3, and 4. aack low in address termination keeper must be actively driven. see notes 3 and 4. artry low bidi address termination keeper 5k ? pull-up to ov dd required. see notes 3 and 4. bg low in address arbitration keeper active driv er or pull-down. see notes 3 and 4. br low out address arbitration keeper chip ac tively drives. see notes 3 and 4. bvsel n/a in i/o level keeper 5k ? set high or low as design. see notes 3 and 4. ci low out transfer attributes keeper see note 1. see notes 3 and 4. ckstp_in low in interrupt/resets keeper must be actively driven. see notes 3 and 4. ckstp_out low out interrupt/resets keeper see notes 3 and 4. dbg low in data arbitration keeper active driver or tie low. see notes 3 and 4. dh0-31 n/a bidi data bus keeper see notes 1, 3, and 4. dl0-31 n/a bidi data bus keeper see notes 1, 3, and 4. gbl low bidi transfer attributes keeper see notes 1, 3, and 4. hreset low in interrupt/resets keeper active driver. see notes 2, 3, and 4. int low in interrupt/resets keeper active driv er or pull-up. see notes 3 and 4. l1_tstclk n/a in lssd not enabled 5k ? pull-up to ov dd required. l2_tstclk/dbwo low in lssd not enabled 5k ? pull-up to ov dd required. lssd_mode low in lssd not enabled 5k ? pull-up to ov dd required. mcp low in interrupt/resets keeper active driv er or pull-up. see notes 3 and 4. pll _cfg (0-3) n/a in clock control keeper as required pull-up/pull-down, as required. see notes 3 and 4. qack low in status/control keeper must be actively driven. see notes 3 and 4. qreq low out status/control keeper chip actively drives. see notes 3 and 4. notes: 1. depends on the system design 2. hreset , sreset , and trst are signals used for esp and riscwatch ? to enable proper operation of the debuggers. logical and gates should be placed between these signals and the powerpc 750cxr. see figure 6-3 on page 40. 3. keepers prevent floating nets from entering the forbidden zone and causing a slight amount of additional current flow in the input circuits. 4. if other components on the 60x bus call for a signal to maintain a particular level while it is not being actively driven, th en an external resistor (or equivalent) must be used. do not rely on the keepers.
data sheet powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 system design information page 39 of 43 sreset low in interrupt/resets keeper active driver or pull-up. see notes 2, 3, and 4. sysclk low in clock control keeper no resistor by design active driver. see notes 3 and 4. ta low in data termination keeper active driver. see notes 3 and 4. tbst low bidi transfer attributes keeper 5k ? pull-up to ov dd required. see notes 3 and 4. tck high in jtag not enabled external. pulldown tdi high in jtag enabled high internal- enabled 50 a @ 2.5v, 25 a@1.8v is the pull-up cur- rent for the internal resistor. tdo high out jtag keeper see notes 3 and 4. tea low in data termination keeper active driv er or pull-up. see notes 3 and 4. tms high in jtag enabled high internal- enabled 50 a @ 2.5v, 25 a@1.8v is the pull-up cur- rent for the internal resistor. trst low in jtag enabled high internal- enabled 50 a @ 2.5v, 25 a@1.8v is the pull-up cur- rent for the internal resistor. see note 2. ts low bidi address start keeper 5k ? pull-up to ov dd required. tsiz0_tsiz2 n/a out transfer attributes keeper see notes 1, 3, and 4. tt0-4 n/a in transfer attributes keeper see notes 1, 3, and 4. wt low out transfer attributes keeper see notes 1, 3, and 4. table 6-3. input-output usage (continued) powerpc 750cxr signal name active level input/ output usage group i/o with internal resistors level protect required external resistor comments notes: 1. depends on the system design 2. hreset , sreset , and trst are signals used for esp and riscwatch ? to enable proper operation of the debuggers. logical and gates should be placed between these signals and the powerpc 750cxr. see figure 6-3 on page 40. 3. keepers prevent floating nets from entering the forbidden zone and causing a slight amount of additional current flow in the input circuits. 4. if other components on the 60x bus call for a signal to maintain a particular level while it is not being actively driven, th en an external resistor (or equivalent) must be used. do not rely on the keepers.
data sheet powerpc ? 750cxr risc microprocessor preliminary system design information page 40 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 6.6 thermal manage ment information this section provides thermal management information for the pbga package for air cooled applications. proper thermal control design is primarily dependent upon the system-level design and air flow. 6.6.1 thermal assist unit the thermal sensor in the thermal assist unit (tau) has not been characterized to determine the basic uncalibrated accuracy. the relationship between the actual junction temperature and the temperature indicated by thrm1 and thrm2 is not well known. ibm recommends calibration of the tau in these devices before use. calibration methods are discussed in the ibm application note calibrating the thermal assist unit in the ibm25ppc750l processors . although this note was written for the 750l, the calibration methods discussed in this document also apply to the 750cxr. 6.6.2 heat sink considerations the powerpc 750cxr package will support a maximum normal load of 2.2kg. this load includes the heat sink and any forces used to position or fasten the heat sink. figure 6-3. ibm riscwatch jtag to hreset , trst , and sreset signal connector hreset from riscwatch system hreset hreset to 750cx trst to 750cx sreset to 750cx sreset from riscwatch system sreset trst from riscwatch note: see notes for table 6-3 on page 38.
data sheet preliminary powerpc ? 750cxr risc microprocessor 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 system design information page 41 of 43 6.6.3 internal package conduction resistance for the pbga, described in table 4-3 on page 16, the primary intrinsic conduction thermal resistance paths are as follows. die junction-to-case thermal resistance jc die junction-to-lead thermal resistance jb die junction-to-ambient thermal resistance ja figure 6-4 depicts the primary heat transfer path for this package. 6.7 operational and design considerations 6.7.1 level protection a level protection feature is included in the powerpc 750cxr. the level protection feature is available only in the 1.8v bus mode. this feature prevents ambiguous floating reference voltages by pulling the respective signal line to the last valid or nearest valid state. for example, if the i/o voltage level is closer to ov dd , the circuit pulls the i/o level to ov dd ; if the i/o level is closer to gnd, the i/o level is pulled low. this self-latching circuitry ?keeps? the floating inputs defined and avoids meta-stability. in table 6-3, these signals are defined as ?keeper? in the level protect column. figure 6-4. pbga package thermal model external resistance external resistance internal resistance (note the internal versus external package resistance.) radiation convection radiation convection die/case ( jc ) printed-circuit board package/leads ( jb ) chip junction ja
data sheet powerpc ? 750cxr risc microprocessor preliminary system design information page 42 of 43 750cxr_dd4.0_dev_gen_4_mkt.fm february 28, 2005 the level protect circuitry provides no additional leakage current to the signal i/o; however, some amount of current must be applied to the ?keeper? node to overcome the level protection latch. this current is process dependent, but in no case is the current required over 100 a. this feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce costs. 6.7.2 64- or 32-bit data bus mode typical operation is considered to be in 64-bit data bus mode. mode setting is determined by the state of the mode signal (qack ) at the transition of hreset from its active to inactive state (low to high). if qack is low when hreset transitions from active to inactive, 64-bit mode is selected. if qack is high when hreset transitions from active to inactive, 32-bit mode is selected. 6.7.3 60x bus operation selection between 1.8v and 2.5v i/o is accomplished using the bvsel pin. if bvsel is set low then the 1.8v mode is enabled. if bvsel is set high, then the 2.5v mode is enabled. 6.7.4 d bwo /l2_tstclk one pin has two functions: dbwo and l2_tstclk dependent upon the lssd_mode pin. when the lssd_mode pin is low, the dbwo /l2_tstclk pin is set to l2_tstclk function which is used during the manufacturing process for testing. when the lssd_mode pin is pulled to the high state, the dbwo /l2_tstclk pin is set to dbwo which is identical to those descriptions given in earlier versions of the powerpc ? 750cxr risc microprocessor user?s manuals . 6.7.5 chkstp_out /clkout chkstp_out /clkout share a common pin. chkstp_out is the normal function of this pin. the system clock or processor clock may be viewed by setting the appropriate bits in hardware implementation-dependent register 0.
data sheet powerpc ? 750cxr risc microprocessor revlog.fm february 28, 2005 revision log page 43 of 43 revision log rev contents of modification apr. 14, 2003 version 0.1 initial preliminary, advanced release. may 23, 2003 version 0.2 modified the following: changed 750cxe to 750cxr throughout document figure 1-1 part number key table 3-1 general parameters table 4-5 power consumption (also added a note with initial guidelines for power numbers) table 4-7 60x bus input timing specifications figure 4-3 input timing diagram table 4-8 60x bus output ac timing specifications figure 4-7 jtag clock input timing diagram july 11, 2003 version 0.2 modified the following: changed cxr to cxr throughout the document updated supported frequency range information added information to table 4-5 power consumption changed table 6-1 powerpc 750cxr microprocessor pll configuration july 15, 2003 version 0.2 made changes based on review comments. changed table 6-1 powerpc 750cxr pll configuration july 17, 2003 version 0.2 made changes based on review comments. july 18, 2003 version 0.2 made changes based on review comments. september 11, 2003 version 1.0 release version. november 24, 2003 version 1.0 added 500 and 533 mhz information. january 12, 2004 version 1.0 corrected formatting problem. no technical changes. february 13, 2004 version 1.1 in section 1. general information, changed reference to revision 4.0 of the 750cxr. in figure 1-1. ibm part number key, added ?p = plastic/laminate ball grid array? to package type. changed max voltage to 1.9 for sysclk input low vo ltage in table 4-4 dc electrical specifications. added columns for 500 and 533 mhz in table 4-5. power consumption. changed max processor frequency to 533 mhz in table 4-6 clock ac timing specifications. march 2, 2004 removed plastic/laminate bga in figure 1-1 part number key added 466 mhz to performance sort in figure 1-1 part number key added ?< 500 mhz? to first line of table 4-2 recommended operating conditions revised table 4-5. power consumption february 28, 2005 removed ?preliminary? from page headers. updated legal page.

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